(a) Field of the Invention
The present invention relates to a semiconductor device with a metal line and a method of forming the same. More particularly, the present invention relates to a metal line in a semiconductor device and a method of forming the same by using a low-k (low dielectric constant) insulation layer.
(b) Description of the Related Art
As semiconductor devices have become highly integrated, logic devices are also required to have higher speed and higher integration. In order to enhance integration of a semiconductor device, metal lines therein are required to be miniaturized.
However, a higher speed of a semiconductor device is not easily achieved due to line delay.
An aluminum alloy is conventionally used as a wiring material in LSI (Large Scale Integration), but copper (Cu) has recently been used as a wiring material in LSI because copper has low resistivity and high strength against EM (electro-migration).
However, since copper is hard to etch and since it can be oxidized during manufacturing processes, a damascene process has recently been used for forming a copper line.
A damascene process is performed by the following steps; firstly, an inter-connection groove in which an upper wire will be formed is formed on an insulation layer, and a via hole connecting the upper wire with a lower wire or substrate is also formed on an insulation layer; and secondly, a metal line is formed by performing a CMP (Chemical Mechanical Polishing) process for copper which is filled in the inter-connection groove and via hole.
A low-k (low dielectric constant) insulation layer is used with a copper line in such a damascene process, because it may increase the speed of a device by reducing a parasitic capacitance between metal lines and reduce cross-talk of a device.
Hereinafter, a conventional method of forming a metal line in a semiconductor device using a dual damascene process will be described with reference to FIG. 1A to FIG. 1F.
FIG. 1A to FIG. 1F are cross-sectional views showing sequential states of a method of forming a metal line in a semiconductor device using a dual damascene process.
Referring to FIG. 1A, a lower conductive layer 110, an etch stop layer 120, a lower insulation layer 130, and an upper insulation layer 140 are sequentially formed.
Referring to FIG. 1B, a photosensitive layer pattern 150 having an opening D1-1 for a via hole is formed on the upper insulation layer 140.
However, when a lithography process is performed for the photosensitive layer pattern 150, a photoresist tail (not shown) may be created thereon. A photoresist tail may occur when a via hole is miniaturized due to miniaturization of a metal line, when a depth of a via hole to be etched is increased, and when a thickness of a photosensitive layer used as an etching barrier is also increased.
As shown in FIG. 1C, a via hole is formed up to the etch stop layer 120 by selectively etching the upper insulation layer 140 and lower insulation layer 130 while using the photosensitive layer pattern 150 as an etch mask. Thereafter, the photosensitive layer pattern 150 is removed by performing an ashing process.
Referring to FIG. 1D, a photosensitive layer 160 is deposited on the entire surface of the upper insulation layer 140 including the via hole, and the photosensitive layer 160 is left only in the via hole by performing blanket etching. When subsequent processes for forming an inter-connection groove are performed, the photosensitive layer 160 remaining in the via hole is used as a barrier layer for preventing removal of or damage to the etch stop layer 120 below the via hole.
Subsequently, a photosensitive layer pattern 170 having an opening is formed on the upper insulation layer 140. The opening has the same width as a predetermined width D1-2 of an inter-connection groove. Thereafter, the upper insulation layer 140 is etched in the predetermined thickness of a metal line by using the photosensitive layer pattern 170 as an etch mask.
Referring to FIG. 1E, the photosensitive layer pattern 170 and photosensitive layer 160 are removed by an ashing process, and the lower conductive layer 110 is exposed by removing the etch stop layer 120 below the via hole through blanket etching.
According to a conventional method of forming a metal line in a semiconductor device, when the lower insulation layer 130 and the upper insulation layer 140 are formed as low-k (low dielectric constant) insulation layers including an organic polymer, they are damaged by oxygen plasma that is used in two ashing processes for the photosensitive layer patterns 150 and 170.
More particularly, when the lithography process for the photosensitive layer pattern 170 having the same width as an inter-connection groove is not performed properly, a rework process for removing the photosensitive layer pattern should be performed. However, during the rework process, the insulation layers 130 and 140 having an organic polymer are severely damaged because they are already exposed at both sidewalls of the inter-connection groove and the via hole.
Thereafter, as shown in FIG. 1F, a barrier metal layer 180 is formed in the inter-connection groove and the via hole, and a metal line is finally formed by polishing conductive materials filling the inter-connection groove and the via hole through a CMP process.
Such a conventional dual damascene process for forming a metal line may induce a photoresist tail, and it may induce severe damage to an insulation layer during ashing and re-ashing processes.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.